Dr. Shyamapada Mukherjee


Assistant Professor
Office : Room No. 26, Department of CSE
             Email: shyamamukherji[at]gmail[dot]com
“Every day we have plenty of opportunities to get angry, stressed or offended. But what you’re doing when you indulge these negative emotions is giving something outside yourself power over your happiness. You can choose to not let little things upset you”—–Joel Osteen       
“I love to do research, I want to do research, I have to do research, and I hate to sit down and begin to do research—I always try to put it off just as long as I can. ….Isn’t there something I can (must?) do first? Shouldn’t I sharpen my pencils perhaps?”

I Want to be a Mathematician
“Trust in the Lord with all your heart and lean not on your own understanding; in all your ways acknowledge Him, and He will make your paths straight”.

Never say NO, Never say, ‘I cannot’, for you are INFINITE. All the power is WITHIN you. You can do anything. —Swami Vivekananda




  • B. E, M.Tech,  PhD


My research interests lie primarily in the area of computer-aided-design of integrated circuits, specifically centered in algorithms for placement and routing for high-performance VLSI circuits and different FPGA architectures. In addition to this I have started working in the following areas:

  • Verification and Testing in VLSI  Design
  • Designing IoT devices
  • Machine Learning Applications
  • Gait Analysis


  1. Shyamapada Mukherjee, Suchismita Roy. Nearly-2-SAT Solutions for Segmented Channel Routing, IEEE Transaction on Computer Aided-Design of Integrated Circuits and Systems, Volume 35, Issue 1, Jan 2016, Pages 128-140. (SCI)
  2. Shyamapada Mukherjee, Suchismita Roy, SAT based solutions for detailed routing of island style FPGA architectures, Microelectronics Journal, Elsevier, Volume 46, Issue 8, August 2015, Pages 706-715. (SCI)
  3. Shyamapada Mukherjee, Suchismita Roy. Via-Aware Dogleg Router using Boolean Satisfiability, J CIRCUIT SYST COMP 26, 1750064 (2017) [24 pages] DOI: http://dx.doi.org/10.1142/S0218126617500645. (SCI)
  4. Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy. 2013. Congestion Balancing Global Router. VLSI Design and Test, Communications in Computer and Information Science, Springer Berlin Heidelberg, 2013, Volume 382, Pages 223-232. (SCOPUS)
  5. Shyamapada Mukherjee, Suchismita Roy. 2012. Testing the Effect of different Switch Box Architectures on Detailed Routing in FPGA. International Journal of Computer Applications, 2012, Volume iC3S, Number 5, pages 1-5.
  6. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee. 2016. SAT based Rectilinear Steiner Tree Construction. 2nd International Conference on Applied and Theoretical Computing and Communication Technology , IEEE, July 2016.
  7. Shyamapada Mukherjee, Suchismita Roy. 2015. Multi Terminal Nets Routing for Island Style FPGAs using Nearly-2-SAT-Computation. 19th International Symposium on VLSI Design and Test (VDAT), IEEE, June 2015, pages 1-6 .
  8. Shyamapada Mukherjee, Suchismita Roy. 2014. Effect of Relaxed Switching Structures on Detailed Routing of Island Style FPGA. International Conference on Information and Communication Technology for Competitive Strategies, ACM, 2014, Article No. 35, pages 35:1–35:6
  9. Shyamapada Mukherjee, Suchismita Roy. 2013. Graph Colouring Based Multi Pin Nets Detailed Routing for Island Style FPGAs using SAT. International Advance Computing Conference, IEEE, 2013, pages 308-312.
  10. Shyamapada Mukherjee, Suchismita Roy. 2010. SAT Based Multi Pin Net Detailed Routing For FPGA. International Symposium on Electronic System Design, IEEE Computer Society. 2010, Pages 141-146.

Papers Under Review

  1. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, Rectilinear Steiner Tree Construction Techniques using PB-SAT based         Methodology, Integration, the VLSI Journal.
  2. Sharbani Purakayastha, Shyamapada Mukherjee, Lookahead Legalization Based Global Placement for Heterogeneous FPGAs. (Conference)
  3. Prasun Datta and Shyamapada Mukherjee, Global Placement for Large-scale Mixed-size Design VLSI Circuits using Plant Model.  (Conference)
  4. Prasun Datta and Shyamapada Mukherjee, A Methodological Architecture Aware Routability-Driven Placement for Large Scale Mixed-Size Design Circuits, IEEE Transaction on VLSI Systems.
  5. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, K-Nearest Neighbour Approach with SAT for Rectilinear Steiner Tree Construction. (Conference)


  1. Assistant Professor, Department of Computer Science and Engineering, National Institute of Technology, Silchar, India.July, 2016–till Date
  2. Assistant Professor, Department of Computer Science and Information Systems, Birla Institute of Technology and Science Pilani, Rajasthan India. Dec, 2015–17th July, 2016
  3. Assistant Professor, Department of Computer Application, Dr. B.C. Roy Engineering College, Durgapur, India. March, 2007–Dec, 2015
  4. Lecturer, Department of Computer Science & Engineering, Bengal Institute of Technology & Management, Santiniketan, India. July,2006–February,2007.


       (2007 to 2015) :- Theory of Computation, Compiler Design, Design and Analysis of Algorithms,  Computer Architecture, Operating                                               Systems, Computer Networks

       Semester (July – Dec, 2017):             1. VLSI Design CS 1401 (B.Tech)
                                                                       2. Advanced Data Structure CS 1502 (M.Tech)
       Semester ( Jan – May, 2017):            1. Design and Analysis of Algorithms CS 1306 (B.Tech)
                                                                        2. Introduction to Computing CS 1101 (B.Tech)
       Semester (July – Dec, 2016):            1. VLSI Design CS 1401 (B.Tech)
      B. Tech:   Palm Vein Pattern Authentication System 
     M. Tech: PIGP: Plant Inspired Global Placement of Mixed-sized Hierarchical VLSI Circuits


                      1. Alok Das (Completed)
                      2. Asish Singh (On going)
                      1. Sharbani Purkayastha (On going)
                      2. Rohit Pratap Singh (On going)
                      3. Prasun Datta (On going)
                           4. Sudeshna Kundu(On going)
                           5. Yagnyasenee Sengupta(On going)
Faculty Advisor: CSE 3rd SEM (Jan – June 2017)
Faculty Advisor: CSE 5th SEM (July – Dec 2017)
BTech Coordinator (July 2017 – tilldate)
DUPC Committee member
MTech Admission Committee member
MTech Syllabus Committee mamber